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october 2011 doc id 11265 rev 5 1/14 14 usblc6-2 very low capacitance esd protection features 2 data-line protection protects v bus very low capacitance: 3.5 pf max. very low leakage current: 150 na max. sot-666 and sot23-6l packages rohs compliant benefits very low capacitance between lines to gnd for optimized data integrity and speed low pcb space consumption: 2.9 mm 2 max for sot-666 and 9 mm2 max for sot23-6l enhanced esd protection: iec 61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level esd protection of v bus high reliability offered by monolithic integration low leakage current for longer operation of battery powered devices fast response time consistent d+ / d- signal balance: ? very low capacitance matching tolerance i/o to gnd = 0.015 pf ? compliant with usb 2.0 requirements complies with the following standards: iec 61000-4-2 level 4: ? 15 kv (air discharge) ? 8 kv (contact discharge) figure 1. functional diagram (top view) applications usb 2.0 ports up to 480 mb/s (high speed) compatible with usb 1.1 low and full speed ethernet port: 10/100 mb/s sim card protection video line protection portable electronics description the usblc6-2sc6 and usblc6-2p6 are monolithic application specific devices dedicated to esd protection of high speed interfaces, such as usb 2.0, ethernet links and video lines. the very low line capacitance secures a high level of signal integrity wit hout compromising in protecting sensitive chips against the most stringently characterized esd strikes. sot23-6l usblc6-2sc6 sot-666 usblc6-2p6 1 1 6 2 5 3 4 i/o1 i/o1 gnd v bus i/o2 i/o2 www.st.com
characteristics usblc6-2 2/14 doc id 11265 rev 5 1 characteristics table 1. absolute ratings symbol parameter value unit v pp peak pulse voltage iec 61000-4-2 air discharge iec 61000-4-2 contact discharge mil std883g-method 3015-7 15 15 25 kv t stg storage temperature range -55 to +150 c t j operating junction temperature range -40 to +125 c t l lead solder temperature (10 seconds duration) 260 c table 2. electrical characteristics (t amb = 25 c) symbol parameter test conditions value unit min. typ. max. i rm leakage current v rm = 5.25 v 10 150 na v br breakdown voltage between v bus and gnd i r = 1 ma 6 v v f forward voltage i f = 10 ma 1.1 v v cl clamping voltage i pp = 1 a, 8/20 s any i/o pin to gnd 12 v i pp = 5 a, 8/20 s any i/o pin to gnd 17 v c i/o-gnd capacitance between i/o and gnd v r = 1.65 v 2.5 3.5 pf c i/o-gnd 0.015 c i/o-i/o capacitance between i/o v r = 1.65 v 1.2 1.7 pf c i/o-i/o 0.04
usblc6-2 characteristics doc id 11265 rev 5 3/14 figure 2. capacitance versus voltage (typical values) figure 3. line capacitance versus frequency (typical values) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 c(pf) f=1mhz v =30mv t =25c osc rms j c =i/o-i/o j c =i/o-gnd o data line voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 1 10 100 1000 c(pf) v =30mv t =25c osc rms j v =0v to 3.3v line f(mhz) figure 4. relative variation of leakage current versus junction temperature (typical values) figure 5. frequency response 1 10 100 25 50 75 100 125 t (c) j v =5v bus i[t rm j ] / i [t rm j =25c] 100.0k 1.0m 10.0m 100.0m 1.0g -20.00 -15.00 -10.00 -5.00 0.00 s21(db) f(hz)
technical information usblc6-2 4/14 doc id 11265 rev 5 2 technical information 2.1 surge protection the usblc6-2 is particularly optimized to perform surge protection based on the rail to rail topology. the clamping voltage v cl can be calculated as follow: v cl + = v transil + v f for positive surges v cl - = - v f for negative surges with: v f = v t + r d .i p (v f forward drop voltage) / (v t forward drop threshold voltage) and v transil = v br + r d_transil .i p calculation example we assume that the value of the dynamic resistance of the clamping diode is typically: r d = 0.5 and v t = 1.1 v we assume that the value of the dynamic resistance of the transil diode is typically: r d_transil = 0.5 and v br = 6.1 v for an iec 61000-4-2 surge level 4 (contact discharge: v g = 8 kv, r g = 330 ), v bus = +5 v, and if in first approximation, we assume that: i p = v g / r g = 24 a. so, we find: v cl + = +31.2 v v cl - = -13 v note: the calculations do not take into account phenomena due to parasitic inductances. 2.2 surge protection application example if we consider that the connections from the pin v bus to v cc , from i/o to data line and from gnd to pcb gnd plane are done by tracks of 10 mm long and 0.5 mm large, we assume that the parasitic inductances l vbus , l i/o and l gnd of these tracks are about 6 nh. so when an iec 61000-4-2 surge occurs on data line, due to the rise time of this spike (t r =1ns), the voltage v cl has an extra value equal to l i/o .dl/dt + l gnd .di/dt. the di/dt is calculated as: di/dt = i p /t r = 24 a/ns the overvoltage due to the parasitic inductances is: l i/o .dl/dt = l gnd .di/dt = 6 nh x 24 a/ns = 144 v by taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: v cl + = +31.2 + 144 + 144 = 319.2 v v cl - = -13.1 - 144 - 144 = -301.1 v
usblc6-2 technical information doc id 11265 rev 5 5/14 we can significantly reduce this phenomena with simple layout optimization. it is for this reason that some recommendations have to be followed (see 2.3: how to ensure good esd protection ). figure 6. esd behavior: parasitic phenomena due to unsuitable layout 2.3 how to ensure good esd protection while the usblc6-2 provides high immunity to esd surge, efficient protection depends on the layout of the board. in the same way, with the rail to rail topology, the track from data lines to i/o pins, from v cc to v bus pin and from gnd plane to gnd pin must be as short as possible to avoid overvoltages due to parasitic phenomena (see figure 6. and figure 7. for layout consideration) v bus l i/o l vbus l gnd l i/o l gnd v pin cc v cl v f i/o pin v transil v+v transil f -v f v cl- t = 1 ns r t t t = 1 ns r v cl+ gnd pin data line positive surge negative surge esd surge on data line di dt l i/o + l gnd di dt di dt -l i/o - l gnd di dt di dt v + =v +v + l + l surge > 0 cl transil f i/o gnd v = -v - l - l surge > 0 cl- f i/o gnd di dt di dt di dt di dt di dt rd.ip v v br transil + = figure 7. esd behavior: layout optimiza tion figure 8. esd behavior: measurement conditions unsuitable layout optimized layout 1 1 6 2 5 3 4 1 1 6 2 5 3 4 +5 v in out test board esd surge usblc6-2sc6
technical information usblc6-2 6/14 doc id 11265 rev 5 important: a good precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector). 2.4 crosstalk behavior 2.4.1 crosstalk phenomenon figure 11. crosstalk phenomenon the crosstalk phenomenon is due to the coupling between 2 lines. the coupling factor ( 12 or 21) increases when the gap across lines decr eases, particularly in silicon dice. in the above example the expected signal on load r l2 is 2 v g2 , in fact the real voltage at this point has got an extra value 21 v g1 . this part of the v g1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. this phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. the perturbed line will be more affected if it wo rks with low voltage signal or high load impedance (few k ). figure 9. esd response to iec 61000-4-2 (+15 kv air discharge) figure 10. esd response to iec 61000-4-2 (-15 kv air discharge) vin vout vin vout line 1 line 2 v g1 v g2 r g1 r g2 drivers r l1 r l2 receivers + 1 12 v g1 v g2 + 2 21 v g2 v g1
usblc6-2 technical information doc id 11265 rev 5 7/14 figure 12. analog crosstalk measurements figure 12. shows the measurement circuit for the analog application. in usual frequency range of analog signals (up to 240 mhz) the effect on disturbed line is less than -55 db (see figure 13. ). figure 13. analog crosstalk results as the usblc6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. the frequency response ( figure 5. ) gives attenuation information and shows that the usblc6-2 is well suitable for data line transmission up to 480 mbit/s while it works as a filter for undesirable signals like gsm (900 mhz) frequencies, for instance. network analyser port 2 network analyser port 1 test board vbus usbl c6 -2sc6 100.0k 1.0m 10.0m 100.0m 1.0g - 120.00 - 90.00 - 60.00 - 30.00 0.00 db f (hz)
technical information usblc6-2 8/14 doc id 11265 rev 5 2.5 application examples figure 14. usb 2.0 port application diagram using usblc6-2 figure 15. t1/e1/ethernet protection hub- downstream transceiver + 5v r s r s r s r s r pd r pd r pd r pd protecting bus switch device- upstream transceiver + 3.3v sw 1 r pu v bus d+ d- gnd v bus v bus v bus r x ls/fs + r x ls/fs + r x ls/fs + r x ls/fs + r x hs + r x hs + r x hs + r x hs + t x hs + t x hs + t x hs + t x hs + t x ls/fs + t x ls/fs + t x ls/fs + t x ls/fs + r s r s usb connector t x ls/fs - t x ls/fs - t x ls/fs - t x ls/fs - r x ls/fs - r x ls/fs - r x ls/fs - r x ls/fs - r x hs - r x hs - r x hs - r x hs - t x hs - t x hs - t x hs - t x hs - gnd gnd gnd gnd sw 2 device- upstream transceiver usblc6-4sc6 usblc6-2p6 usblc6-2sc6 + 3.3v sw 1 r pu v bus d+ d- gnd r s r s usb connector sw 2 open closed then open high speed hs open closed full speed fs closed open low speed ls sw 2 sw 1 mode data transceiver smp75-8 smp75-8 tx rx +v cc +v cc 100nf 100nf usblc6-2sc6 usblc6-2sc6
usblc6-2 technical information doc id 11265 rev 5 9/14 2.6 pspice model figure 16. shows the pspice model of one usblc6-2 cell. in this model, the diodes are defined by the pspice parameters given in figure 17. figure 16. pspice model note: this simulation model is available only for an ambient temperature of 27 c. model = dlow model = dhigh vbus li/o lgnd gnd d+in model = dzener ri/o li/o d-in ri/o li/o li/o rgnd ri/o d-out ri/o model = dlow model = dhigh li/o d+out ri/o figure 17. pspice parameters figure 18. usblc6-2 pcb layout considerations dlow dhigh dzener bv 50 50 7.3 cj0 0.9p 2.0p 40p ibv 1m 1m 1m m 0.3333 0.3333 0.3333 rs 0.2 0.52 0.84 vj 0.6 0.6 0.6 tt 0.1u 0.1u 0.1u li/o 750p ri/o 110m lgnd 550p rgnd 60m d+in d+out d-out gnd usblc6-2 d-in v bus 1 c = 100nf bus
ordering information scheme usblc6-2 10/14 doc id 11265 rev 5 3 ordering information scheme figure 19. ordering information scheme usb lc 6 - 2 xxx product designation low capacitance breakdown voltage packages 6 = 6 volts 2 = 2 lines sc6 = sot23-6l p6 = sot-666 number of lines protected
usblc6-2 package information doc id 11265 rev 5 11/14 4 package information epoxy meets ul94, v0 lead-free packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 3. sot-666 dimensions ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.45 0.60 0.018 0.024 a3 0.08 0.18 0.003 0.007 b 0.17 0.34 0.007 0.013 b1 0.19 0.27 0.34 0.007 0.011 0.013 d 1.50 1.70 0.059 0.067 e 1.50 1.70 0.059 0.067 e1 1.10 1.30 0.043 0.051 e0.50 0.020 l1 0.19 0.007 l2 0.10 0.30 0.004 0.012 l3 0.10 0.004 d b l3 l1 e b1 e1 l2 e a a3 figure 20. sot-666 footprint dimensions in mm figure 21. sot-666 marking 0.50 2.60 0.62 0.30 0.99 f
package information usblc6-2 12/14 doc id 11265 rev 5 table 4. sot23-6l dimensions ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.90 1.45 0.035 0.057 a1 0 0.10 0 0.004 a2 0.90 1.30 0.035 0.051 b 0.35 0.50 0.014 0.020 c 0.09 0.20 0.004 0.008 d 2.80 3.05 0.11 0.118 e 1.50 1.75 0.059 0.069 e 0.95 0.037 h 2.60 3.00 0.102 0.118 l 0.10 0.60 0.004 0.024 0 10 0 10 a2 a l h c b e d e e a1 q figure 22. sot23-6l footprint dimensions in mm figure 23. sot23-6l marking 0.95 0.60 1.20 1.10 3.50 2.30 ul26
usblc6-2 ordering information doc id 11265 rev 5 13/14 5 ordering information 6 revision history table 5. ordering information order code marking package weight base qty delivery mode usblc6-2sc6 ul26 sot23-6l 16.7 mg 3000 tape and reel usblc6-2p6 f sot-666 2.9 mg 3000 tape and reel table 6. document revision history date revision changes 14-mar-2005 1 first issue. 07-jun-2005 2 format change to figure 3; no content changed. 20-mar-2008 3 added marking illustrations - figures 21 and 23. added ecopack statement. updated operating junction temperature range in absolute ratings, page 2. technical information section updated. reformatted to current standards. 27-jun-2011 4 updated leakage current for v rm = 5.25 v as specified in usb standard. updated ma rking illustrations figure 21 and figure 23 . 24-oct-2011 5 updated legal statement.
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